//`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/07/20 11:17:34
// Design Name: 
// Module Name: display_time_Divider
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module display_time_Divider(
    input clk_i,
    output reg clk_d
);
    
    
reg [26:0] cnt='d0;
reg [26:0] divideNum='d10_0000;


always@(posedge clk_i)
    cnt<=(cnt>=divideNum)?'d0:(cnt+'d1);


always@(posedge clk_i)
    clk_d<=(cnt<(divideNum+'d1)/'d2);


endmodule
